"Pins", in this case, means the logical ports used to interface one module within an FPGA to another. Think AMBA bus, clock(s), interrupt lines, etc. An FPGA SOC design that currently throws a bunch of different IPs (modules) together to do... something... could do the same with this core thrown in to replace a (classic) Microblaze with only a resynthesis on the hardware side, and a recompile on the software side.